1. Field of the Invention
The present invention relates to a complex band-pass filter for use in a radio receiver such as digital radio receiver, a complex band-pass ΔΣ AD modulator using the same complex band-pass filter, an AD converter circuit using the complex band-pass ΔΣ AD modulator, and a digital radio receiver using the same AD converter circuit.
2. Description of the Related Art
For a high-frequency receiver circuit of a radio communication system such as a mobile telephone or a radio LAN, a low-intermediate frequency (Low-IF) receiver architecture (See, for example, First Non-Patent Document described later) is one of effective applications. When two “one-input and one-output ΔΣ AD modulators” are employed according to this application, the same AD modulators perform AD conversion on not only a signal component but also an image component, and this leads to inefficiency. On the other hand, a complex band-pass ΔΣ AD modulator performs the AD conversion on only the signal component. Therefore, the AD converter can be implemented with lower power consumption and is suitable for this application (See, for example, Second to Fourth Non-Patent Documents described later).
Further, when each of an internal AD converter and an internal DA converter of the ΔΣ AD modulator is constituted as a multi-bit converter, then the requirements for performance of the internal operational amplifier are moderated, and a larger signal-to-noise ratio (SNR) can be implemented by a low-order loop filter. Therefore, the converter with lower power consumption can be implemented. Considering these points, a data-weighted averaging algorithm (referred to as a DWA algorithm hereinafter) has been developed for the complex band-pass modulator (See, for example, Sixth to Eighth Non-Patent Documents described later). In this case, a logic circuit for implementing a DWA algorithm by a circuit is referred to as a DWA logic circuit.
Prior art documents related to the present invention are as follows:
(1) First Patent Document: Japanese Patent Laid-Open Publication No. JP-05-275972-A;
(2) Second Patent Document: Japanese Patent Laid-Open Publication No. JP-11-017549-A;
(3) Third Patent Document: Japanese Patent Laid-Open Publication No. JP-2000-244323-A;
(4) Forth Patent Document: Japanese Patent Laid-Open Publication No. JP-2002-100992-A;
(5) First Non-Patent Document: J. Crols, et al., “Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers”, IEEE Transaction on Circuits and Systems II, Vol. 45, No. 3, pp. 269–282, March 1998;
(6) Second Non-Patent Document: F. Munoz et al., “A 4.7 mW 89.5 dB DR CT Complex ΔΣ ADC with Built-in LPF”, ISSCC Digest of Technical Papers, Vol. 47, pp. 500–501, February 2004;
(7) Third Non-Patent Document: N. Yaghini et al., “A 43 mW CT Complex ΔΣ ADC with 23 MHz of Signal Band width and 68.6 SNDR”, ISSCC Digest of Technical Papers, Vol. 47, pp. 502–503, February 2005;
(8) Fourth Non-Patent Document: S. A. Jantzi et al., “Quadrature bandpass ΣΔ modulator for digital radio”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, pp. 1935–1949, December 1997;
(9) Fifth Non-Patent Document: Akira Hayakawa et al., “Design of Discrete-Time Multi-bit Complex Bandpass ΣΔ AD modulators”, Technical Report of IEICE (The Institute of Electronics, Information and Communication Engineers), IEICE Electronics Society Technical Committee on Integrated Circuits and Devices, Osaka, Jul. 13, 2004;
(10) Sixth Non-Patent Document: H. San et al., “An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass Delta-sigma AD Modulators”, IEEE 17th International Conference on VLSI Design, pp. 151–156, Mumbai, India, January 2004;
(11) Seventh Non-Patent Document: H. San et al., “A Noise-shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass ΔΣ AD Modulators”, IEICE Transactions of Fundamentals, Vol. E87-A, No. 4, pp. 792–800, April 2004;
(12) Eighth Non-Patent Document: Hiroki Wada et al., “Mapping from a DWA Algorithm into Circuit for Multi-bit Complex Band-pass ΔΣ AD Modulators”, Report of Meeting of IEEJ(The Institute of Electrical Engineers of Japan) on Electronic Circuits, ECT-04-47, pp. 1–6, Hakodate, Jun. 25, 2004;
(13) Ninth Non-Patent Document: L. Longo et al., “A 15 b 30 kHz Bandpass Sigma-Delta Modulator”, ISSCC Digest of Technical Papers, pp. 226–227, February 1993.;
(14) Tenth Non-Patent Document: R. Schreier, “Quadrature Mismatch-shaping”, Proceedings of ISCAS, Vol. 4, pp. 675–678, May 2002;
(15) Eleventh Non-Patent Document: J. Riches et al., “Mismatch Cancellation in Quadrature Bandpass ΔΣ Modulators Using an Error Shaping Technique”, IEEE Transactions on Circuits and Systems II, Vol. 49, pp. 73–85, February 2002;
(16) Twelfth Non-Patent Document: L. Breems et al., “A Quadrature Data-dependent DEM Algorithm to Improve Image Rejection of a Complex ΔΣ Modulator”, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1879–1886, December 2001;
(17) Thirteenth Non-Patent Document: R. Maurino et al., “Multibit Quadrature Sigma-Delta Modulator with DEM Scheme”, Proceedings of ISCAS, Vol. 1, pp. 1136–1139, May 2004; and
(18) Fourteenth Non-Patent Document: K. W. Martin et al., “Complex Signal Processing is Not Complex”, IEEE Transactions on Circuits and Systems I, Vol. 51, pp. 1823–1836, September 2004.
First of all, configurations and problems of a first-order complex band-pass filter according to a first prior art and a second-order complex band-pass filter according to a second prior art employed in a complex band-pass ΔΣ AD modulator will be described.
FIG. 19 is a circuit diagram showing a configuration of the first-order complex band-pass filter according to the first prior art. Referring to FIG. 19, the first-order complex band-pass filter includes two adders SU1 and SU2, and two delay circuits DE1 and DE2 each of which delays an input signal by a time interval corresponding to one clock signal to output the delayed input signal. The first-order complex band-pass filter performs a predetermined filtering on an inputted I signal Iin and an inputted Q signal Qin, and outputs an I signal lout and a Q signal Qout represented by the following equations:Iout(n)=Iin(n−1)−Qout(n−1)  (1), andQout(n)=Qin(n−1)+Iout(n−1)  (2),
where “n” denotes a parameter indicating a processing timing. The first-order complex band-pass filter thus configured according to the first prior art has the following problems. The mismatching in the element parameters is caused between an I circuit part including the adder SU1 and the delay circuit DE1, and a Q circuit part including the adder SU2 and the delay circuit DE2. The mismatching leads to deterioration in the precisions of the output signals lout and Qout. Further, as apparent from FIG. 19, there are signal lines crossing each other between the I and Q circuit parts. As a result, when the layout of the complex band-pass filter on an integrated circuit is designed, wirings are disadvantageously complicated, and also, a chip area disadvantageously increases.
FIG. 20 is a circuit diagram showing a configuration of a complex band-pass ΔΣ AD modulator including a one-bit second-order complex band-pass filter according to a second prior art. The complex band-pass Δ93 AD modulator includes I and Q circuit parts. The I circuit part includes the following:
(1) multipliers AP1, AP11, AP21 and AP31 each of an amplifier (a number within each symbol indicates an amplification factor, and this can be applied hereinafter);
(2) adders SU1 and SU11;
(3) delay circuits DE1 and DE11 each delaying an input signal by a time interval corresponding to one clock signal;
(4) an AD converter ADCI; and
(5) DA converters DAC1 and DAC3.
The Q circuit part includes the following:
(1) multipliers AP2, AP12, AP22 and AP32 each of an amplifier;
(2) adders SU2 and SU12;
(3) delay circuits DE2 and DE12 each delaying an input signal by a time interval corresponding to one clock signal;
(4) an AD-converter ADCQ; and
(5) DA converters DAC2 and DAC4.
The complex band-pass ΔΣ AD modulator thus configured according to the second prior art has the following problems. The mismatching in the element parameters is caused between the I and Q circuit parts. This mismatching leads to not only deterioration in the precisions of output signals Iout and Qout from the modulator, but also deterioration in the signal-to-noise ratio (SNR). Further, as apparent from FIG. 20, there are the signal lines crossing one another between the I and Q circuit parts. As a result, when the layout of the complex band-pass filter on an integrated circuit is designed, wirings are disadvantageously complicated and also a chip area disadvantageously increases.
FIG. 21 is a circuit diagram showing a configuration of a complex band-pass ΔΣ AD modulator including a multi-bit second-order complex band-pass filter, according to a third prior art. This is a second-order complex band-pass ΔΣ AD modulator according to a prior art previously considered by the inventors of the present invention, and is disclosed in, for example, the Fifth Non-Patent Document. Referring to FIG. 21, amplification factors are set as follows: a1=⅓, b1=−⅔, a2= 3/2, and b2=2. The second-order complex band-pass ΔΣ AD modulator includes a second-order complex filter, two three-bit AD converters ADCI and ADCQ, and four three-bit DA converters DAC1, DAC2, DAC3 and DAC4.
In order to suppress the influence of nonlinearity of each of the multi-bit DA converters DAC1, DAC2, DAC3 and DAC4, the DWA algorithm developed by the inventors of the present invention is applied to the same. In addition, three multiplexers MU1-101, MU1-102 and MU1-103, and DWA logic circuits DWA1 and DWA2 are added to a feedback path formed by the four DA converters DAC1, DAC2, DAC3 and DAC4 (See, for example, the Sixth to Eighth Non-Patent Documents). A detailed configuration of each of the multiplexers MU1-101, MU1-102 and MU1-103 is similar to that of the multiplexer MU1 shown in FIG. 3. The detailed configurations of the DWA logic circuits DWA1 and DWA2 are shown in FIGS. 8 and 9, respectively, and will be described later.
The relationship among input signals and output signals inputted to and outputted from the complex band-pass ΔΣ AD modulator shown in FIG. 21 is represented by the following equation:
                                          I            out                    +                      jQ            out                          =                                            z                              -                2                                      ⁡                          [                                                                    1                    2                                    ⁢                                      (                                                                  I                                                  i                          ⁢                                                                                                          ⁢                          n                                                                    +                                              jQ                                                  i                          ⁢                                                                                                          ⁢                          n                                                                                      )                                                  +                                                                            (                                              z                        -                        j                                            )                                        2                                    ⁢                                      (                                                                  E                        I                                            +                                              jE                        Q                                                              )                                                              ]                                .                                    (        3        )            
In addition, the relationship among internal signals of the complex band-pass ΔΣ AD modulator shown in FIG. 21 is represented by the following equations:I1(n+1)=a1·Iin(n+1)+b1·DAC1(n+1)−Q1(n)  (4),Q1(n+1)=a1·Qin(n+1)+b1·DAC2(n+1)+I1(n)  (5),I2(n+1)=a2·I1(n)+b2·DAC3(n+1)−Q2(n)  (6), andQ2(n+1)=a2·Q1(n)+b2·DAC4(n+1)+I2(n)  (7).
The DAC converters DAC1 and DAC4 constitute a feedback circuit that feeds back an output signal from the AD converter ADC1. The DAC converters DAC2 and DAC3 constitute a feedback circuit that feeds back an output signal from the AD converter ADC2.
The following two problems are caused in the case of the configuration of the complex band-pass ΔΣ AD modulator shown in FIG. 21:
(1) Complicated layout: as shown in FIG. 21, in internal complex band-pass filters CBF1 and CBF2, and the feedback circuits formed by four-channel DA converters constituting I and Q circuit parts of the complex band-pass ΔΣ AD modulator, signal lines of I and Q signals cross each other in many portions. As a result, wirings are longer on the layout of an IC chip, a power consumption of a drive circuit is larger, and a chip area increases.
(2) The mismatching in the element parameters between the I and Q circuit parts: when the circuits of the complex band-pass ΔΣ AD modulator shown in FIG. 21 are implemented on the chip, the mismatching of analog circuit characteristics is caused between the I circuit part located at the upper stage of a forward path and the Q circuit part located at the lower stage of thereof due to manufacturing irregularities of element parameters. Then the quantization noise in an image band enters a signal band. This results in deterioration in the precision of the entire modulator (Concretely speaking, this leads to deterioration in the SNR (See Appendix 1 described later)). Several methods for reducing the influence of the mismatching in the element parameters between the I and Q circuit parts have been proposed (See, for example, the Tenth to Thirteenth Non-Patent Documents). These methods are not always effective for and directly applied to the configuration of the modulator proposed by the inventors of the present invention.